Memory cell including stacked gate sidewall patterns and...

Details Memory cell including stacked gate sidewall patterns and... Memory cell including stacked gate sidewall patterns and...

2006-03-21

2006-03-21

Huynh, Andy (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S316000, C257S320000, C257S321000

Reexamination Certificate

active

07015541

ABSTRACT:
A memory cell and a method for fabricating same. The memory cell comprises a source region and a drain region formed in a semiconductor substrate and a channel region defined between the source and drain regions. Charge storage layers are formed the channel region. A gate insulating layer is formed on the channel region between the charge storage layers, and a gate electrode is formed on the gate insulating layer and the charge trapping storage layers.

REFERENCES:
patent: 5768192 (1998-06-01), Eitan
patent: 5969383 (1999-10-01), Chang et al.
patent: 6011725 (2000-01-01), Eitan
patent: 6218695 (2001-04-01), Nachumovsky
patent: 6335554 (2002-01-01), Yoshikawa
patent: 6348711 (2002-02-01), Eitan
patent: 6673677 (2004-01-01), Hofmann et al.
patent: 2001-230332 (2001-08-01), None
patent: WO 02/11145 (2002-02-01), None

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