Memory cell including single event upset rate reduction circuitr

Details Memory cell including single event upset rate reduction circuitr Memory cell including single event upset rate reduction circuitr

1988-09-07

1990-04-03

Moffitt, James W.

Static information storage and retrieval

Systems using particular element

Flip-flop

G11C 1140

Patent

active

049146297

ABSTRACT:
The rate of single event upset in a memory cell is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly.

REFERENCES:
patent: 4725981 (1988-02-01), Rutledge
patent: 4797804 (1989-01-01), Rockett, Jr.
"DMSP Dosimetry Data: A Space Measurement and Mapping of Upset Causing Phenomena", E. G. Gussenhower, et al., IEEE Trans. Nuclear Science, vol. NS-34, pp. 1251-1255 (1987).
"An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM", H. T. Weaver, et al., IEEE Trans. Nuclear Science, vol. NS-34, pp. 1281-1286. (1987).
"Alpha Particle Induced Soft Errors in Dynamic Memories", T. C. May, et al., IEEE Trans. Electronic Devices, vol. ED-26, p. 2 (1979).
"CMOS RAM Cosmic Ray Induced Error Rate Analysis", J. C. Pickel, et al., IEEE Trans. on Nuclear Science, vol. NS-28, pp. 3962-3967 (1981).

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