Memory cell including an emitter follower and emitter...

Details Memory cell including an emitter follower and emitter... Memory cell including an emitter follower and emitter...

2008-09-18

2010-11-30

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Semiconductive

C365S189050

Reexamination Certificate

active

07843721

ABSTRACT:
A memory device including a static random access memory (SRAM) cell comprising junction field effect transistors (JFETs) has been disclosed. The memory cell includes a first bipolar junction transistor (BJT) for driving a bit line at logic levels having a potential outside the potential range in which the SRAM cell operates. An amplifier including a level translator circuit provides a level shifting operation on the data provided by the bit line to provide level shifted data having a voltage swing within the potential range in which the SRAM cell operates. The level translator circuit includes a second BJT. In this way, fast read operation of a SRAM cell comprising JFETs may be provided.

REFERENCES:
patent: 5567961 (1996-10-01), Usagawa et al.
patent: 2009/0057728 (2009-03-01), Boyle
patent: 2009/0168508 (2009-07-01), Kapoor et al.
Wingard et al., Circuit Techniques for Large CSEA SRAM's, IEEE Journal of Solid-State Circuits, Jun. 1992, pp. 908-919, vol. 27, No. 6.

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