Memory cell having improved read stability

Details Memory cell having improved read stability Memory cell having improved read stability

2006-09-12

2006-09-12

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189011, C365S230050

Reexamination Certificate

active

07106620

ABSTRACT:
A memory cell for use in a memory array includes a storage element for storing a logical state of the memory cell, a write circuit and a read circuit. The write circuit is operative to selectively connect a first node of the storage element to at least a first write bit line in the memory array in response to a write signal for selectively writing the logical state of the memory cell. The read circuit includes a substantially high impedance input node connected to the storage element and an output node connectable to a read bit line of the memory array. The read circuit is configured to generate an output signal at the output node which is representative of the logical state of the storage element in response to a read signal applied to the read circuit. The memory cell is configured such that the write circuit is disabled during a read operation of the memory cell so as to substantially isolate the storage element from the first write bit line during the read operation. A strength of at least one transistor device in the storage element is separately optimized relative to a strength of at least one transistor device in the write circuit and/or the read circuit.

REFERENCES:
patent: 5239501 (1993-08-01), Matsui et al.
patent: 5847990 (1998-12-01), Irrinki et al.
patent: 6807081 (2004-10-01), Nii
patent: 6845059 (2005-01-01), Wordeman et al.
patent: 6903962 (2005-06-01), Nii
patent: 2004/0156228 (2004-08-01), Becker

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