Memory cell having combination raised source and drain and...

Details Memory cell having combination raised source and drain and... Memory cell having combination raised source and drain and...

2005-04-22

2008-08-19

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE21430, C257SE21619, C257SE21634, C438S300000

Reexamination Certificate

active

07414277

ABSTRACT:
A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of raised bitlines, where the bitlines have a lower portion formed by a first process and an upper portion formed by a second process.

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patent: 2005/0176220 (2005-08-01), Kanemoto

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