Memory cell having a shared read/write line

Details Memory cell having a shared read/write line Memory cell having a shared read/write line

1996-03-06

1997-07-08

Nelms, David C.

Static information storage and retrieval

Addressing

Multiple port access

365239, 36518904, 365221, 365187, G11C 1140

Patent

active

056469039

ABSTRACT:
A DRAM memory having shared read/write lines. The DRAM memory is comprised of an array of 3T memory cells. Data is digitally stored in the form of capacitors that are either charged or discharged. Horizontal data lines are used to convey data bits to be stored in the array of memory cells. Vertical read/write lines are used to perform both read and write functions. Activating a single read/write line causes a bit of data from a memory cell to be placed onto a corresponding data line. Simultaneously, an inverted copy of that data bit is stored in an adjacent memory cell. Hence, instead of having a separate read line and a separate word line for each memory cell, the present invention has a dual function read/write word line.

REFERENCES:
patent: 4935896 (1990-06-01), Matsumura et al.
patent: 5513139 (1996-04-01), Butler
"The New IEEE Standard Dictionary of Electrical and Electronics Terms", Fifth Edition, The Institute of Electrical and Electronic Engineers, Inc. 345 East 47th Street, New York, NY 10017-2394, Copyright 1993, p. 1064.
Neil H. E. Weste, Kamran Eshraghian, "Principles of CMOS VLSI Design", Copyright 1985, pp. 353-354.
Lance A. Glasser & Daniel W. Dobberpuhl, "The Design and Analysis of VLSI Circuits", Copyright 1985, pp. 393-395.
Edward J. McCluskey, "Logic Design Principles", Copyright 1986, pp. 526-527 .

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