Memory cell for storing at least three logic states

Details Memory cell for storing at least three logic states Memory cell for storing at least three logic states

1997-10-08

1999-03-30

Nguyen, Viet Q.

Static information storage and retrieval

Systems using particular element

Flip-flop

365188, 365148, 365156, 365174, G11C 1100

Patent

active

058896970

ABSTRACT:
A memory cell for storing data having at least three logic states includes a pair of storage devices and third-level storage and refresh circuitry coupled to a pair of storage nodes. The storage devices maintain multi-level signals representative of first and second logic states at the pair of storage nodes. To store a third logic state, the third-level storage and refresh circuitry maintain the multi-level signals at both storage nodes at substantially equal intermediate levels.

REFERENCES:
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5218569 (1993-06-01), Banks
patent: 5293560 (1994-03-01), Harari
patent: 5311076 (1994-05-01), Park et al.
patent: 5390143 (1995-02-01), Manning
patent: 5635731 (1997-06-01), Ashida
patent: 5757051 (1998-05-01), Wu et al.
patent: 5761110 (1998-06-01), Irrinki et al.

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