Memory cell error recovery

Details Memory cell error recovery Memory cell error recovery

2002-04-05

2004-08-31

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including signal comparison

C365S200000, C365S210130, C365S185210

Reexamination Certificate

active

06785169

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices relating to memory applications susceptible to errors including soft errors.
BACKGROUND
In a variety of memory applications, such as SRAM, DRAM, non-volatile memory, thin capacitively coupled thyristor (TCCT) applications, other RAM applications and other memory applications such as CAM, dual-port, FTFO, etc., circuitry used to stare data can experience conditions that result in the stored data being corrupted. Errors common to memory cells include one or more cells sticking at a particular value (e.g. stuck-at-1), a write-zero pulse not being wide enough for a particular bit, a read-one circuit noise margin not being enough, and others. One particular type of error that has presented challenges to memory applications is a soft error. Soft errors occur when data stored in a memory cell is upset in a non-permanent manner, such as when stored data is changed to an incorrect value by a particle interaction. For example, the value of a memory cell may be changed from a “1” to a “0” value or from a “0” to a “1” value. These changes can result in incorrect data and inhibit the performance of memory cells.
The rate at which soft errors occur is referred to as the soft error rate, or SER. The SER can be calculated empirically, or else by first simulating the charge created at each node, and then simulating the device behavior to find the charge distribution conditions that lead to a soft error. The spectrum of each node that can result in a charge that causes an error is found, and the fluxes of the relevant parts of each spectrum are integrated to find the total flux and the probability of a bit error. Assuming the errors are probabilistically independent (which is not always the case), the resulting probability of failure can be represented by the equation:
N
bit
×P
1-bit
where N
bit
is the number of bits in the device and P
1-bit
is the probability related to the failure of a bit.
A variety of sources, such as alpha particles, cosmic rays, high-energy, and thermal neutrons, can cause soft errors. These sources can be generated in a variety of manners. For instance, alpha particles may be generated by contamination in metal layers, ceramic portions, and solder contacts of an integrated circuit die, and they generally create a small charge (e.g., 15 fC/micron) and a relatively high flux (e.g., 0.001-0.002/h-cm
2
). Cosmic background radiation, such as background radiation generated at sea level, generates cosmic rays that typically exhibit a relatively low flux and a relatively high charge. Thermal neutrons, which include very low energy cosmic background neutrons, generally exhibit a relatively high flux and a moderate charge and cause fission in borophosphosilicate gas (BPSG) films.
Memory cells typically exhibit a critical charge, or Qcrit, at which a soft error will occur (ie., a charge that will upset the cell). The charge created by these and other sources can be collected in a portion of the cell and when the collected charge (Qcollected) exceeds Qcrit, a soft error occurs.
If BPSG is used, the SER is typically dominated by fission. However, in many modem applications, and particularly in DRAM applications, BPSG is reduced or eliminated. In the absence of BPSG and where Qcrit is high the SER is dominated by cosmic rays because they generate a relatively large amount of charge. In applications where BPSG is absent and Qcrit is low, alpha particles dominate the SER.
Qcrit for flipping a “0” to a “1” is approximately the same as Qcrit for flipping a “1” to a “0” in symmetric memory cells such as 6-transistor SRAM. However, in asymmetric memory cells, Qcrit01 (Qcrit to flip a bit from “0” to “1”) is very different from Qcrit10 (Qcrit to flip a bit from a “1” to “0”). For example, in TCCT base memory cells the Qcrit01 is significantly less than Qcrit10, and, a soft error detection and correction method which assumes that all soft errors are “0” to “1” flips can be used.
In each of the above and in other applications, SER and other error rates continue to present challenges to the continued advancement of the semiconductor industry.
SUMMARY
The present invention is directed to overcoming the above-mentioned challenges and others related to the types of devices and applications discussed above and in other memory cells. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a memory arrangement is adapted for error recovery using first and second (mirror) bits. The memory arrangement includes a first asymmetric memory cell and a mirror asymmetric memory cell, each asymmetric memory cell being adapted to receive and store a same bit in response to a write operation. An output circuit detects and compares the bits stored at the first and mirror asymmetric memory cells. An error is detected when the bits stored at the first and mirror cells are different (e.g., when one of the cells has been upset by an error, such as excess charge near the cell). In response to detecting an error on either the first or the mirror cell, the output circuit is adapted to provide an output corresponding to the bit received and stored. In one implementation, this detection and correction scheme involves performing a logical AND operation between the first cell and the mirror cell in the case that errors are presumed to flip a “0” into a “1” only, and in the case that errors are presumed to flip a “1” into a “0” only, a logical OR operation is performed between the first cell and the mirror cell. This scheme is able to detect and correct an error to either one of the first cell or the mirror cell.
In another example embodiment, the present invention is directed to a method for recovering from errors in a memory arrangement having first and mirror asymmetric memory words, each word comprising one or more cells. During a write cycle, bits provided (written) to the first asymmetric memory word are also provided to the mirror asymmetric memory word. Between consecutive write cycles, memory cells from each word can become upset. The bits stored at each memory cell are compared for a read operation, and when the values stored at the first and mirror memory cells are different, a bit corresponding to the received and stored bit at the first asymmetric memory word is read out. In one implementation, this detection and correction scheme involves performing a logical AND operation between the first word and the mirror word in the case that errors are presumed to flip a “0” into a “1” only, and in the case that errors are presumed to flip a “1” into a “0” only, a logical OR operation is performed between the first word and the mirror word. This scheme is able to detect and correct all errors in which either one or none of any two corresponding memory cells in the first word and mirror word have an error.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.


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