Memory cell employing reduced voltage

Details Memory cell employing reduced voltage Memory cell employing reduced voltage

2011-01-04

2011-01-04

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Read/write circuit

Common read and write circuit

C365S189150, C365S189160, C365S227000

Reexamination Certificate

active

07864600

ABSTRACT:
A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.

REFERENCES:
patent: 5177706 (1993-01-01), Shinohara et al.
patent: 5253199 (1993-10-01), Gibson
patent: 5535159 (1996-07-01), Nii
patent: 5808933 (1998-09-01), Ross et al.
patent: 6016268 (2000-01-01), Worley
patent: 6201758 (2001-03-01), Morishima et al.
patent: 6519195 (2003-02-01), Kanno et al.
patent: 6888202 (2005-05-01), Kang et al.
patent: 7106620 (2006-09-01), Chang et al.
patent: 7120072 (2006-10-01), Ye et al.
patent: 7136296 (2006-11-01), Luk et al.
patent: 7259986 (2007-08-01), Bhavnagarwala et al.
patent: 7313012 (2007-12-01), Chuang et al.
patent: 7359275 (2008-04-01), Wu
patent: 7440313 (2008-10-01), Abeln et al.
patent: 7583543 (2009-09-01), Sumitani
patent: 2001/0043487 (2001-11-01), Nii et al.
patent: 2003/0223276 (2003-12-01), Yamaoka et al.
patent: 2005/0036394 (2005-02-01), Shiraishi
patent: 2007/0097756 (2007-05-01), Hirota et al.
patent: 2007/0242498 (2007-10-01), Chandrakasan et al.
patent: 2008/0151653 (2008-06-01), Ishikura et al.
patent: 2009/0168496 (2009-07-01), Mikan et al.
patent: 2009/0168508 (2009-07-01), Kapoor et al.

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