Memory cell driver circuits

Details Memory cell driver circuits Memory cell driver circuits

2007-06-26

2007-06-26

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S094000, C365S063000

Reexamination Certificate

active

11169106

ABSTRACT:
A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.

REFERENCES:
patent: 6515344 (2003-02-01), Wollesen
patent: 6686791 (2004-02-01), Zheng et al.
patent: 6693481 (2004-02-01), Zheng
patent: 7126871 (2006-10-01), Marr et al.
patent: 7158412 (2007-01-01), Rodgers et al.
patent: 2002/0141249 (2002-10-01), Tedrow et al.
patent: 2006/0126377 (2006-06-01), Honda et al.

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