Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1997-07-25
1999-03-23
Nelms, David
Electronic digital logic circuitry
Multifunctional or programmable
Array
365194, G11C 700
Patent
active
058869360
ABSTRACT:
A memory cell data equalization control circuit is provided for sensing data stored in a memory cell. The memory cell data equalization control circuit outputs the sensed data through a bit line and an input/output line in an input/output stage of a semiconductor memory device. The circuit includes a feedback unit for generating a plurality of feedback signals in accordance with a signal output from a main amplifier coupled to the input/output line and an equalizer for equalizing the input/output line in accordance with a first feedback signal. The circuit self-equalizes the data input/output line using the feedback signals generated according to the output from the main amplifier to enhance the data input/output speed. The circuit further controls the coupling of the bit line and the data line to reduce electric power consumption. Further, the circuit prevents instability in an applied system caused by glitching of an address signal.
REFERENCES:
patent: 4807190 (1989-02-01), Ishii et al.
patent: 5268874 (1993-12-01), Yamauchi
patent: 5740115 (1998-04-01), Ishibashi et al.
Le Thong
LG Semicon Co. Ltd.
Nelms David
LandOfFree
Memory cell data line equalization controlling circuit for semic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory cell data line equalization controlling circuit for semic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell data line equalization controlling circuit for semic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2132922