Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-12-17
2001-05-08
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000, C257S303000, C365S149000, C365S182000
Reexamination Certificate
active
06229169
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
Memory cell configurations, in particular DRAM configurations, ROM configurations, EPROM configurations and EEPROM configurations, have a multiplicity of memory cells that are usually disposed in the form of a matrix. In this case, the individual memory cells can each be driven via a bit line and a word line. The memory cells each have a storage element in which information is stored. The information is stored, for example, by a charge stored in a storage capacitance, by a charge stored on a floating gate, or by properties of a transistor, for example the threshold voltage, or by the presence or absence of a conductive connection to the bit line.
In order to read out the information, the individual memory cells are driven sequentially via the associated word line and bit line and the information is read out by voltage or current evaluation (see, for example, Y. Nakagome et al., IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, 1991, pages 465 to 470). With regard to the reading speed, current evaluation is preferable to voltage evaluation but it requires an increased outlay in terms of circuitry. In order to accelerate the reading operation, it is frequently the case that a plurality of memory cells, for example 256, are combined to form a cell block. The individual cell blocks are then read out in parallel. However, the read-out operation in the individual cell block is still carried out sequentially.
In electrically writable memory cell configurations, for example DRAM configurations or EEPROM configurations, in order to write in information, the respective memory cell is likewise driven via the associated bit line and the word line. At the same time, a voltage level corresponding to the information to be written in is applied to the bit line. The information is written sequentially to all the memory cells. In this case, the bit line must each time undergo charge reversal from one voltage state to the other voltage state. This is associated with a consumption of electrical power which is found to be disturbing particularly when the memory cell configuration is used in mobile equipment such as, for example, mobile telephones, notebook computers, database computers or PDA (personal digital assistant).
In DRAM configurations, moreover, the problem arises that the stored information must be refreshed again at regular time intervals. For this purpose, the information is initially read sequentially from the memory cells and then written back. An undesirable power consumption occurs in this case, too.
A further problem in the context of DRAM configurations is the storage density, which increases from memory generation to memory generation. Associated with this is the requirement for an increased packing density, that is to say a reduction in the space requirement per memory cell. German Patent DE 19 519 160 C1 discloses a DRAM cell configuration which can be fabricated with a memory cell area of 4F
2
, where F is the minimum structure size that can be fabricated using the respective technology. In this case, a vertical MOS transistor is provided for each memory cell, the first source/drain region of the transistor is connected to a storage node of a storage capacitor. A channel region of the transistor is enclosed annularly by a gate electrode, and the second source/drain region of the transistor is connected to a buried bit line. The gate electrodes of neighboring vertical MOS transistors along a word line adjoin one another and jointly form the word line.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell configuration, method for fabricating it and methods for operating it which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which can be driven in an improved way. In particular, the intention is to be able to fabricate the memory cell configuration with a storage density as is required in the gigabit generations.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration, including: a semiconductor substrate having a main surface; a multiplicity of memory cells disposed in the semiconductor substrate, the memory cells each having a storage element and at least one selection transistor disposed vertically to the main surface of the semiconductor substrate and connected to the storage element; and a first word line and a second word line crossing one another and driving the memory cells.
A semiconductor substrate having a multiplicity of memory cells is provided. The memory cells each have at least one selection transistor that is vertical with respect to a main surface of the semiconductor substrate and is connected to a storage element. The selection transistor is preferably connected between a bit line and the storage element. However, the bit lines may also be connected up differently. The memory cells can each be driven via a first word line and a second word line, the first word line and the second word line crossing one another. A memory cell is driven only via the first word line and the second word line. As a result, bit lines can be read out in parallel.
In the case of an electrically writable memory cell configuration, the memory cells are likewise driven in each case via the first word line and the second word line. The bit line is used only for the application of the voltage level corresponding to the information, and not for the purpose of driving. Therefore, in order to write in an item of information corresponding to a predetermined voltage level, it is possible to apply the predetermined voltage level to all the bit lines. Those memory cells in which the associated item of information is supposed to be stored are driven via the first word lines and the second word lines. This information is written to all the corresponding memory cells in a clock cycle. In order to write in a digital information item, therefore, two operations are sufficient: firstly, parallel writing in of a “one” and, secondly, parallel writing in of a “zero”. As a result, the writing operation is considerably accelerated in comparison with the prior art. Furthermore, the bit line must undergo charge reversal only as often as corresponds to the number of different information items. In the case of the digital information item, the bit line only has to undergo charge reversal twice. The power consumption is thereby reduced.
In the case of a DRAM configuration, this is also utilized for the refreshing of the information. In this case, the stored information is preferably read out via a shift register. The data word stored in the shift register is subsequently used to drive the first word lines and the second word lines, the bit line being put at the respective voltage levels.
As a result of the significantly smaller number of necessary charge-reversal operations of the bit line in comparison with the prior art, the power consumption in the course of writing in and also in the course of refreshing information is distinctly reduced.
A suitable semiconductor substrate is, in particular, a monocrystalline silicon wafer or the monocrystalline silicon layer of an SOI substrate.
All storage elements that are customarily used in memory cell configurations are suitable as the storage element. In particular, suitable storage elements are those which have MOS transistors having different electrical properties, as are frequently used in ROM configurations, line interruptions, as are used in ROM configurations, fuses, MOS transistors with floating gate and also storage capacitances.
It lies within the scope of the invention to configure the memory cell configuration as a DRAM configuration. In this case, not only can the advantage of the faster data access in the course of reading and writing information be utilized but also the advantage of the smaller power consumption in the course of writing and refreshing the information. In the DRAM configuration, the storage element is preferably confi
Basse Paul-Werner
Hofmann Franz
Krautschneider Wolfgang
Risch Lothar
Rosner Wolfgang
Greenberg Laurence A.
Infineon - Technologies AG
Kang Donghee
Lerner Herbert L.
Stemer Werner H.
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