Memory cell comprising one MOS transistor with an isolated...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257SE29019, C257SE29025, C438S294000

Reexamination Certificate

active

07541636

ABSTRACT:
A memory cell with one transistor on a floating body region isolated by its lower surface by a junction. According to the present invention, the junction is non-planar and, for example, includes a protrusion directed towards the transistor surface.

REFERENCES:
patent: 6288425 (2001-09-01), Adan
patent: 6661042 (2003-12-01), Hsu
patent: 7061032 (2006-06-01), Kajiyama
patent: 7158410 (2007-01-01), Bhattacharyya et al.
patent: 2004/0061148 (2004-04-01), Hsu
patent: 2005/0040463 (2005-02-01), Wang
patent: 2007/0013007 (2007-01-01), Kusunoki et al.
French Search Report from French Patent Application 05/51836, filed Jun. 30, 2005.
Villaret A. et al., “Mechanisms of Charge Modulation in the Floating Body of Triple-Well nMOSFET capacitor-Less DRAMs” Microelectronic Engineering, Elsevier Publishers BV., Amsterdam, NL, vol. 72, No. 1-4, Apr. 2004, pp. 434-439, XP004499525 ISSN: 0167-9317.
Ranica R. et al., “A One Transistor Cell on Bulk Substrate (IT-bulk) for low-cost and high density e-DRAM” VLSI Technology, 2004. Digest of Technical Papers 2004 Symposium on Honolulu, HI, USA Jun. 15-17, 2004, pp. 128-129, XP010732820 ISBN: 0-7803-8289-7.

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