Memory cell circuits, devices, systems and methods of operation

Details Memory cell circuits, devices, systems and methods of operation Memory cell circuits, devices, systems and methods of operation

1991-06-24

1994-03-08

Hille, Rolf

Static information storage and retrieval

Addressing

Multiple port access

365154, 365182, 365188, 365190, 364754, 257903, 257904, G11C 800, G11C 1134, G06F 1500, H01L 2711

Patent

active

052933490

ABSTRACT:
A memory cell constructed in accordance with the present invention includes a node operable to present an electrical level representing a first state or a second state. Further included is a first switching device having a first terminal connected to the node such that if the first switching device were to close, the electrical level at the node would be connected to a second terminal of the first switching device. Additionally, second and third switching devices are provided both having first and second terminals and both operable to switch as a function of the state at the node. Finally, a single control switching device is provided in association with the second and third switching devices wherein a control signal switches the control switching device such that the state at the node may be determined by connecting to the first terminals of the second and third switching devices.

REFERENCES:
patent: 4660177 (1987-04-01), O'Connor
patent: 4723226 (1988-02-01), McDonough et al.
patent: 4933899 (1990-06-01), Gibbs
patent: 4984204 (1991-01-01), Sato et al.
patent: 5068830 (1991-11-01), Plants et al.
IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct., 1987, "The Twin-Port Memory Cell", O'Connor, P,712-P,720.

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