Memory cell circuit for executing specific tests on memory cells

Details Memory cell circuit for executing specific tests on memory cells Memory cell circuit for executing specific tests on memory cells

1998-04-28

2000-08-22

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

711220, G01R 3128

Patent

active

06108803&

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor memory device (hereafter called RAM) capable of being read and written to, and to a memory test circuit for performing tests on products having such RAM installed.
Conventionally, a memory test circuit has been used to test the RAM of a DRAM, etc. The RAM tests are performed taking into consideration the interrelation between each bit (memory cell) stored in a plurality of memory cells constituting the RAM, and the operation of a decoder built into the memory circuit. Therefore, the RAM tests perform a test on each memory cell by designating memory cells by successively inputting address signals pointing to the memory cells constituting the RAM in a specified sequence. There are many sequential patterns (hereafter called test patterns) for indicating each memory cell address. For example, test patterns known as "CHECKERBOARD," "MARCHING," "GALLOPING," etc.
A conventional memory test circuit for testing a RAM is shown in FIG. 8. This memory circuit 1 is comprised of a memory 10, an internal clock control circuit 12 (hereafter called an internal clock circuit or clock circuit), a first selector 14, a second selector 16 and a third selector 18.
The memory 10 is comprised of a RAM, and has address input terminals 20, a read signal input terminal 22, a write signal input terminal 24 and a data input/output terminal 26. An address signal An is input to the address input terminals 20 by a tester (not shown) exlusively for an external memory test of the memory circuit 1. A read signal is input to the read signal input terminal 22 and a write signal is input to the write signal input terminal 24.
The internal clock control circuit 12 is provided to drive the memory circuit 10 at the time of normal operation. The internal clock control circuit 12 is provided with a test signal input terminal 28, address signal output terminals 30, a read signal output terminal 32, a write signal output terminal 34 and a data terminal 36. The address signal output terminals 30 of the internal clock control circuit 12 are connected to the address input terminals 20 of the memory 10 via the first selector 14. During normal operation, memory cells within the memory 10 are designated by an address signal output from the address signal output terminals 30.
The read signal output terminal 32 of the internal clock control circuit 12 is connected to the read signal input terminal 22 of the memory 10 via the second selector 16. During normal operation, a read signal is output from the read signal output terminal 32.
The write signal output terminal 34 of the internal clock control circuit 12 is connected to the write signal input terminal 24 of the memory 10 via the third selector 18. During normal operation, a write signal is output from the write signal output terminal 34.
The data terminal 36 of the internal clock control circuit 12 is connected to an external data bus 38 and to the data input/output terminal 26 of the memory 10. During normal operation, data output from the data terminal 36 is input from the data input/output terminal 26 to the memory 10 in response to a write signal output from the write signal output terminal 34 (for example, when this write signal goes to a high level). Also during normal operation, data output from the data input/output terminal 26 of the memory 10 is input from the data terminal 36 to the internal clock control circuit 12 in response to a read signal output from the read signal output terminal 32 (for example, when the read signal goes to a high level).
A test signal RAMTEST is input to the test signal input terminal 28 of the internal clock control circuit 12. The potential level of the test signal RAMTEST is a low potential level (hereinafter termed level "0") during normal operation and a high level (hereinafter termed level "1") during testing. During testing, the output of the data terminal 36 of the internal clock control circuit 12 can have one of three states (level "0", level "1" or a high impedance state) and beco

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patent: 5357620 (1994-10-01), Suzuki
patent: 5386523 (1995-01-01), Crook et al.

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