Memory cell capable of storing more than two logic states by usi

Details Memory cell capable of storing more than two logic states by usi Memory cell capable of storing more than two logic states by usi

1996-12-23

1999-11-09

Zarabian, A.

Static information storage and retrieval

Systems using particular element

Ternary

365100, 365105, G11C 1156

Patent

active

059826592

ABSTRACT:
A process which enables storage of more than two logic states in a memory cell. In one embodiment, a via is used to couple a diode between a word read line and a data read line. The via has a resistance which is set to one of a plurality of values at the time of manufacture. When the word read line is asserted, the voltage drop sustained across the via is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

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