Memory cell array with specific placement of field stoppers

Details Memory cell array with specific placement of field stoppers Memory cell array with specific placement of field stoppers

2011-01-25

2011-01-25

Toledo, Fernando L (Department: 2895)

Static information storage and retrieval

Floating gate

C365S149000, C365S182000, C365S185130, C365S185170, C365S185180, C365S230060, C438S158000, C438S257000, C711S101000, C257S059000, C257S306000, C257S309000, C257S311000, C257S314000, C257S315000, C257S321000, C257S405000, C257S410000, C257S905000, C257S908000, C257SE29162

Reexamination Certificate

active

07876610

ABSTRACT:
A plurality of first transistors formed on a substrate share a gate electrode. Isolation regions isolate the plurality of first transistors from one another. In the region where the plurality of first transistors, an impurity region is formed in such a manner that it includes the source and drain regions of the plurality of first transistors and that the depth of the impurity region is greater than the depth of the source and drain regions. The impurity region sets the threshold voltage of the first transistors.

REFERENCES:
patent: 5946230 (1999-08-01), Shimizu et al.
patent: 2005/0265109 (2005-12-01), Goda et al.
patent: 2002-324400 (2002-11-01), None
U.S. Appl. No. 12/338,417, filed Dec. 18, 2008, Kato, et al.

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