Memory cell array semiconductor integrated circuit device

Details Memory cell array semiconductor integrated circuit device Memory cell array semiconductor integrated circuit device

1995-06-06

1997-08-05

Yoo, Do Hyun

Static information storage and retrieval

Systems using particular element

Flip-flop

365182, 365205, G11C 1140

Patent

active

056549148

ABSTRACT:
Memory cells having a stable write operation are formed in an array on a CMOS gate array semiconductor substrate. Each memory cell includes mutually adjacent transistors from a first pair of complementary conductivity type MOS transistor rows. These transistors are used to form a flip-flop and first and second access gates. The memory cell further includes mutually adjacent MOS transistors from a second pair of complementary conductivity type MOS transistor rows. These transistors are used to form an inverter and a third access gate connected to the output of the inverter. The input of the inverter is connected to one end of the flip-flop. The inputs of the first and second access gates are connected to bit lines through which complementary data signals are applied. The gates of the first and second access gate transistors are connected to a write word line. The third access gate is connected to a read-out signal providing bit line, and the gate of the third access gate MOS transistor is connected to a read word line.

REFERENCES:
patent: 4447891 (1984-05-01), Kadota
patent: 5334880 (1994-08-01), Abadeer et al.
patent: 5379260 (1995-01-01), McClure
patent: 5471420 (1995-11-01), Nii et al.

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