Memory cell array having improved channel characteristics

Details Memory cell array having improved channel characteristics Memory cell array having improved channel characteristics

1997-02-27

1999-01-12

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257506, 438257, H01L 2976, H01L 29788

Patent

active

058594523

ABSTRACT:
A memory cell array with an active region which has first portions and fifth portions which are at both ends thereof and a third portion which is the middle portion thereof. The first, third and fifth portions are parallel to each other with a certain spacing. The first and third portions are interconnected by a second portion sloped toward a side of the third portion. The third portion and fifth portions are interconnected by a fourth portion sloped upward from the other side of the third portion. Source regions are formed in the first and fifth portions and fifth portion of the active region. A drain region is formed in the third portion of the active region. Channel regions are formed in the second portion and fourth portion of the active region. Floating gates are disposed over each of the channel regions. A pair of control gates is disposed over the floating gates.

REFERENCES:
patent: 4918501 (1990-04-01), Komori et al.
patent: 5293331 (1994-03-01), Hart et al.
patent: 5559735 (1996-09-01), Takashi Ono Masami Ikegami

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