Memory cell array and method of forming the same

Details Memory cell array and method of forming the same Memory cell array and method of forming the same

2007-09-25

2007-09-25

Purvis, Sue A. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C438S238000, C438S242000

Reexamination Certificate

active

11152793

ABSTRACT:
A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

REFERENCES:
patent: 5945707 (1999-08-01), Bronner et al.
patent: 6566187 (2003-05-01), Willer et al.
patent: 6656807 (2003-12-01), Bronner et al.
patent: 2005/0003308 (2005-01-01), Frohlich et al.
Kim, et al., “The Breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor (RCAT) for 88 nm feature size and beyond,” 2003 Symposium on VLSI Technology Dig. of Tech. Papers.

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