Memory cell array

Details Memory cell array Memory cell array

2006-11-21

2006-11-21

Elms, Richard (Department: 2824)

Static information storage and retrieval

Hardware for storage elements

Shields

C365S149000, C365S150000

Reexamination Certificate

active

07139184

ABSTRACT:
A memory cell array includes memory cells, bit lines running along a first direction, word lines running along a second direction perpendicular to the first direction, and continuous active area lines, wherein transistors are at least partially formed in the active area lines. The transistors electrically couple corresponding memory cells to corresponding bit lines via bit line contacts, and the transistors are addressed by the word lines. The bit line contacts are formed in a region generally defined by an intersection of a bit line and a corresponding active area line. Neighboring bit line contacts which are connected with one active area line are connected with neighboring bit lines. Consequently, one active area line is crossed by a plurality of bit lines.

REFERENCES:
patent: 5502320 (1996-03-01), Yamada
patent: 6419948 (2002-07-01), Blume et al.
patent: 6545904 (2003-04-01), Tran
patent: 6894915 (2005-05-01), Tran
patent: 7020039 (2006-03-01), Tran et al.
patent: WO 01/01489 (2001-01-01), None

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