Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-09-08
2001-01-30
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S330000, C257S332000, C257S335000, C257S336000, C257S344000
Reexamination Certificate
active
06180979
ABSTRACT:
BACKGROUND OF THE INVENTION
In order to store large volumes of data, for example for DP (data processing) applications or for the digital storage of music or images, use is mainly made at present of memory systems which have mechanically moved parts such as, for example, hard disc memories, floppy discs or compact discs. The moved parts are subject to mechanical wear. Furthermore, they require a comparatively large volume and permit only slow data access. Moreover, since they are sensitive to vibrations and position and have a comparatively high power consumption for their operation, these memory systems can be used in mobile systems only to a limited extent.
In order to store relatively small volumes of data, semiconductor-based read-only memories are known. These are often realized as a planar integrated silicon circuit in which MOS transistors are used as memory cells. The transistors are selected via the gate electrode, which is connected to the word line. The input of the MOS transistor is connected to a reference line and the output is connected to a bit line. During the read operation, it is assessed whether or not a current is flowing through the transistor. The logic values zero and one are assigned correspondingly. The storage of zero and one is effected in technical terms in that no MOS transistor is produced or no conductive connection to the bit line is realized in memory cells in which the logic value assigned to the state “no current flow through the transistor” is stored. As an alternative, MOS transistors which have different threshold voltages due to different dopant concentrations in the channel region can be realized for the two logic values.
These semiconductor-based memories permit random access to the stored information. The electrical power required to read the information is distinctly less than in the case of the abovementioned memory systems having mechanically moved parts. Since no moved parts are required, mechanical wear and sensitivity to vibrations are no longer a problem here either. Semiconductor-based memories can therefore be used for mobile systems as well.
The silicon memories described generally have a planar structure. A minimum area requirement thus becomes necessary for each memory cell and is 4 F
2
in the most favorable case, F being the smallest structure size that can be produced with the respective technology.
A read-only memory cell arrangement whose memory cells comprise MOS transistors is disclosed in German reference DE 42 14 923 A1. These MOS transistors are arranged along trenches in such a way that a source region adjoins the bottom of the trench, a drain region adjoins the surface of the substrate and a channel region adjoins the side and bottom of the trench both vertically with respect to the surface of the substrate and parallel to the surface of the substrate. The surface of the channel region is provided with a gate dielectric. The gate electrode is designed as a side covering (spacer). The logic values zero and one are differentiated by different threshold voltages, which are effected by channel implantation. During the channel implantation, the implanting ions impinge on the surface of the respective trench at an angle such that implantation is deliberately effected only along one side due to shading effects of the opposite side. In this memory cell arrangement, the word lines run as spacers along the sides of the trenches.
Japanese reference JP-A 4-226071 discloses a further memory cell arrangement, which comprises vertical MOS transistors arranged on the sides of trenches as memory cells. In this case, diffusion regions which in each case form the source/drain regions of the vertical MOS transistors run on the bottom of trenches and between adjacent trenches. The word lines, which comprise the gate electrodes of the vertical MOS transistors, run perpendicularly to the trenches. The threshold voltage of the vertical MOS transistors is set by means of angled implantation.
U.S. Pat. No. 4,663,644 discloses a memory cell arrangement whose memory cells comprise vertical MOS transistors. These vertical MOS transistors are each arranged on the sides of trenches. The word lines, which each comprise the gate electrodes of the vertical MOS transistors, are arranged in the trenches. Two word lines are arranged in each trench. The bit lines are realized as conductor tracks on the surface of the substrate. The contact between the bit lines and the respective source/drain regions which adjoin the surface of the substrate is realized via a contact hole. The source/drain regions which adjoin the bottom of the trenches are realized as a continuous doped layer and are put at the reference potential. In this memory cell arrangement, the information is stored in the form of threshold voltages, having different levels, of the MOS transistors. The different threshold voltages are realized by different dopant concentrations in the channel region of the MOS transistors. In order to form an increased dopant concentration in the channel region, a doped layer is deposited and is structured in such a way that sides in which increased dopant concentrations are to be formed remain covered by the structured dopant layer. The channel regions having an increased dopant 25 concentration are formed by outdiffusion of the structured dopant layer.
SUMMARY OF THE INVENTION
The problem underlying the invention is that of specifying a semiconductor-based memory cell arrangement in which an increased storage density is achieved and which can be produced with few production steps and a high yield. Furthermore, it is intended to specify a method for the production of such a memory cell arrangement.
In the memory cell arrangement according to the invention, memory cells which each comprise an MOS transistor which is vertical with respect to the main area are provided in a substrate. A substrate made of monocrystalline silicon or the silicon layer of an SOI substrate is preferably used as the substrate. The vertical MOS transistors have different threshold voltages depending on the stored information.
For the purpose of reading out the information, the MOS transistors are driven at a voltage level at which the MOS transistors having a lower threshold voltage conduct and those having a higher threshold voltage do not conduct.
Strip-like trenches which essentially run in parallel are provided in the substrate. Strip-like doped regions, which are doped by a second conductivity type which is opposite to the first, are arranged on the bottom of the trenches and on the main area between adjacent trenches. Gate dielectrics are in each case arranged on the sides of the trenches. Word lines are provided which run transversely with respect to the trenches and comprise gate electrodes for the vertical MOS transistors in the region of the sides of the trenches. The vertical MOS transistors are in each case formed by two strip-like, doped regions adjoining the same side of one of the trenches, which doped regions act as source/drain region, the trench side arranged in between, the gate dielectric and the part of one of the word lines arranged thereabove. The strip-like doped regions are used as bit or reference line during operation of the memory cell arrangement.
For the purpose of realizing the different threshold voltages, memory cells in which a predetermined information item is stored have a dopant region in the upper region of the side of the trench, the extent of which dopant region perpendicular to the main area is smaller than the depth of the trenches. The dopant regions are preferably doped by the same conductivity type as the channel regions, but with an increased dopant concentration. The threshold voltage rises in this case. They can also be doped by the opposite conductivity type, in which case the threshold voltage then decreases.
The invention makes use of the finding that the threshold voltage of an MOS transistor can also be set by a locally inhomogeneous dopant concentration in the channel region. The parts of the dopant region and its accurate align
Hofmann Franz
Krautschneider Wolfgang
Willer Josef
Shiff Hardin & Waite
Siemens Aktiengesellschaft
Wojciechowicz Edward
LandOfFree
Memory cell arrangement with vertical MOS transistors and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory cell arrangement with vertical MOS transistors and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell arrangement with vertical MOS transistors and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2479232