Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-15
2002-09-03
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S411000
Reexamination Certificate
active
06445046
ABSTRACT:
Memories in which data is permanently written are required for many electronic systems. Such memories are referred to as, among other things, read-only memories, read memories or read-only memory.
Compact disks are employed as read memories for very large data sets. These are plastic disks with a coating of aluminum in which two types of dot-like depressions are arranged. The information is digitally stored in the arrangement of these depressions. For reading data stored on a compact disk, the disk is mechanically rotated in a read device and the dot-like depressions are scanned Five gigabits of information can be stored on a compact disk.
A read device comprises moving parts that are subject to mechanical wear, that require a comparatively large volume, and that only allow a slow data access. Further, the read device is sensitive to jolts and can therefore be applied in only limited fashion in mobile systems.
Read-only memories on a semiconductor basis, by contrast, allow a random access to the stored information. Over and above this, they can be utilized for mobile systems since a mechanical drive is not required for reading the information. MOS transistors are usually employed in these read-only memories. Whether a current flows through the transistor or not is evaluated in the read process. Stored information is correspondingly allocated. Technically, the storing of the information is usually effected in that the MOS transistors exhibit different cut-off voltages due to different implantations in the channel region.
A storage density that can be achieved in read-only memories on a semiconductor basis is dependent on an area requirement per memory cell.
German Patent Application No. DE 195 10 042 has proposed a read-only memory cell arrangement that comprises MOS transistors arranged in lines. The MOS transistors are series-connected in each line. In order to increase the storage density, neighboring lines are respectively arranged at the floor of strip-shaped longitudinal trenches and at the surface of a substrate between neighboring, strip-shaped longitudinal trenches. Source/drain regions connected to one another are fashioned as an interconnect, doped region. The MOS transistors are read by a line-by-line arive similar to a “NAND” architecture.
The programming of the described memory cell arrangements ensues during manufacture. Memories into which data can be written by electrical programming, however, are required for many applications. The storing of information in electrically programmable memory cell arrangements is usually effected in that a floating gate that can be charged with an electrical charge or a in that double layer of SiO
2
and Si
3
N
4
as gate dielectric at whose boundary surface electrical charge carriers can be held fast at traps is provided between the gate and the channel region of the MOS transistors. The cut-off voltage of the MOS transistor is dependent on the charge located on the floating gate or, the traps. This property is utilized for electrical programming (see, for example, S. M. Sze, Semiconductor Devices, John Wiley, pages 486 through 490).
SUMMARY OF THE INVENTION
It is an object of the present to provide a memory cell arrangement that is electrically programmable and that is suitable for storing large data sets. It is further object of the invention to provide a method for the manufacture thereof. These objectives are achieved in accordance with the invention in a memory cell arrangement and a method for the manufacture thereof.
The memory cell arrangement comprises a number of memory cell lines in a semiconductor substrate. Neighboring memory cell lines are insulated from one another.
The memory cell lines respectively comprise a first doped region and a second doped region. A gate dielectric and a number of gate electrodes arranged next to one another are arranged at a principal surface of the semiconductor substrate between the first doped region and the second doped region. The spacing between neighboring gate electrodes is thereby less than the dimensions of the gate electrodes parallel to the connecting line between the first doped region and the second doped region. The gate dielectric contains a material having charge carrier traps.
Traps have the properties of trapping charge carriers, specifically electrons. For electrical programming, the gate electrodes are wired such that charge carriers corresponding to the information to be stored proceed into the gate dielectric under the gate electrode and are held fast by the traps. Since the charge carriers are trapped in the traps, the information is durably stored. The programmed memory cell arrangement therefore represents a read-only memory cell arrangement. The programming can ensue both by Fowler-Nordheim-tunneling as well by hot electron injection. Charge carriers can be removed from the traps by reversing the polarities in the Fowler-Nordheim tunneling, so that the programming of the memory cell arrangement can be modified.
The invention is based on the following considerations: when driving a line in which series-connected MOS transistors are arranged in the sense of an “NAND” architecture, the gate electrodes of the MOS transistors are wired such that all MOS transistors except the selected MOS transistors conduct, regardless of the cut-off voltage of the individual transistor that is not selected. This is effected in that a voltage is applied to the gate electrode that is higher than the highest cut-off voltage that occurs. The gate electrode of the selected MOS transistor, by contrast, is charged with a voltage that lies between the cut-off voltages of the MOS transistors. An evaluation is made to determine whether a current flows across the series-connected MOS transistors or not. When a current flows, then the information corresponding to the lower cut-off voltage is stored in the selected MOS transistor. When no current flows, then the information is stored corresponding to the higher cut-off voltage.
The invention makes use of the principle that most source/drain regions of these MOS transistors act merely as a conductive connection between neighboring, conductive channels upon read-out. A doped region corresponding to a source/drain region is therefore arranged only at the start and at the end of each memory cell line in the inventive memory cell arrangement, gate electrodes arranged tightly side-by-side between these doped regions effecting a space charge zone up to the channel region of the selected gate electrode on the basis of a corresponding wiring. In this way, the space requirement for source/drain regions arranged between two neighboring gate electrodes is eliminated in the memory cell lines. The stray field between neighboring, driven gate electrodes thereby causes the region under the interspaces between neighboring gate electrodes to be made conductive. The spacing between neighboring gate electrodes is preferably amounts to 10 through 100 nm.
In applications wherein the stray field between neighboring, driven gate electrodes is not adequate in order to make the region under the interspace between the neighboring gate electrodes conductive, it lies within the scope of the invention to modulate the dopant distribution at the surface in this region with an opposite doping. A dopant concentration in the region of 10
17
cm
−3
is adequate for this purpose. This dopant concentration is clearly lower than in the first doped region and the second doped region that, like source/drain regions, exhibit a dopant concentration in the range from 10
20
through 10
21
cm
−3
. The opposite doping merely serves for the modulation of neighboring space charge zones. It is not comparable to standard source/drain regions.
For storing data in digital form, different charge quantities are introduced into the gate dielectric under the gate electrodes, so that two different cut-off voltages arise in the arrangement. When the memory cell arrangement is to be utilized for polyvalent logic, then the gate dielectric is charged with different charge quantities in the
Hofmann Franz
Krautschneider Wolfgang
Reisinger Hans
von Basse Paul Werner
Willer Josef
Fourson George
Garcia Joannie Adelle
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
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