Memory cell architecture for reduced routing congestion

Details Memory cell architecture for reduced routing congestion Memory cell architecture for reduced routing congestion

2005-12-27

2005-12-27

Lam, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C365S230060

Reexamination Certificate

active

06980462

ABSTRACT:
An improved memory cell architecture is provided herein for reducing, or altogether eliminating, chip-level routing congestion in System-on-Chip environments. Though only a few embodiments are provided herein, features common to the described embodiments include: the formation of bitlines in a lower-level metallization layer of the memory array, and the use of word lines and ground supply lines, both formed in inter-level metallization layer(s) of the memory array, for effective shielding of the bitlines against routing signals in the chip-level routing layer.

REFERENCES:
patent: 6091629 (2000-07-01), Osada et al.

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