Memory cell and wordline driver for embedded DRAM in ASIC proces

Details Memory cell and wordline driver for embedded DRAM in ASIC proces Memory cell and wordline driver for embedded DRAM in ASIC proces

1994-12-14

1997-02-04

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365149, 257296, G11C 700

Patent

active

056005989

ABSTRACT:
A DRAM charge storage structure including a p-channel access FET in an n.sup.- doped well of a p.sup.- doped substrate, a p.sup.- channel charge storage capacitor, conductive apparatus connecting a gate of the charge storage capacitor to a drain of the FET, and apparatus for applying a boosted word line voltage to a gate of the FET.

REFERENCES:
patent: 4167018 (1979-09-01), Ohba
patent: 5373476 (1994-12-01), Jeon
patent: 5374839 (1994-12-01), Jeon
patent: 5404329 (1995-04-01), Yamagata
patent: 5446688 (1995-08-01), Torimaru

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