Memory cell and read circuit

Static information storage and retrieval – Systems using particular element – Flip-flop

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365177, 365190, 36523005, G11C 1100, G11C 1134, G11C 700, G11C 800

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active

049950010

ABSTRACT:
The present invention relates to a memory cell, and more particularly to a single-bit, dual-port cell, and a single-sided read circuit for use with one or more such cells. The cell may, in one embodiment, be used in a static random access memory (RAM) array, and may be implemented in BICMOS technology on an integrated circuit. The cell has a flip-flop storage unit comprising a CMOS circuit of cross-coupled inverters coupled to dual CMOS pass gates to provide isolation and data transfer. The storage unit is also coupled to a bipolar read line driver in a particular configuration to accomplish rapid bit line pull-up or pulldown for high speed read operation. Several alternative embodiments are disclosed.

REFERENCES:
patent: 3440444 (1969-04-01), Rapp
patent: 3668656 (1972-06-01), Hoggar
patent: 3968480 (1976-07-01), Stein
patent: 4112506 (1978-09-01), Zibu
patent: 4149268 (1979-04-01), Waters
patent: 4262340 (1981-04-01), Sasaki et al.
patent: 4375677 (1983-03-01), Schuermeyer
patent: 4380055 (1983-04-01), Larson
patent: 4387444 (1983-06-01), Edwards
patent: 4395765 (1983-07-01), Moffitt et al.
patent: 4447891 (1984-05-01), Kadota
patent: 4491937 (1985-01-01), Chan
patent: 4499558 (1985-02-01), Mazin et al.
patent: 4527255 (1989-07-01), Keshtbod
patent: 4541076 (1985-09-01), Bowers et al.
patent: 4567577 (1986-01-01), Oliver
patent: 4571703 (1986-02-01), Noda
patent: 4580245 (1986-04-01), Ziegler et al.
patent: 4592023 (1986-05-01), Beranger et al.
patent: 4638461 (1987-01-01), Yonezu et al.
patent: 4639898 (1987-01-01), Sauer
patent: 4644500 (1987-02-01), Yonezu et al.
patent: 4653025 (1987-03-01), Minato et al.
patent: 4654823 (1987-03-01), Charransol et al.
patent: 4654824 (1987-03-01), Thomas et al.
patent: 4660177 (1987-04-01), O'Connor
patent: 4701882 (1987-10-01), Birritella et al.
patent: 4701883 (1987-10-01), Wrathall et al.
patent: 4703458 (1987-10-01), Stipanuk
patent: 4719596 (1988-01-01), Bernstein et al.
patent: 4744056 (1988-05-01), Yu et al.
patent: 4747078 (1988-05-01), Miyamoto
patent: 4779230 (1988-10-01), McLaughlin et al.
patent: 4858183 (1989-08-01), Scharrer et al.
Fields, "Low Voltage Memory Cell", IBM TDB, vol. 22, No. 10, Mar. 1980, pp. 4555-4556.
Denis et al, "Static RAM Cell with Selected Barrier Height Schottky Diodes," IBM TDB, vol. 24, No. 1A, Jun. 1981, pp. 85-87.
Shen, "Multi-Port RAM Cell Structure" IBM TDB, vol. 26, No. 7B, Dec. 1983, pp. 3588-3589.
IBM Technical Disclosure Bulletin, vol. 14, No. 11, p. 3211, Apr. 1972, W. D. Pricer et al., "Memory Array Selection Technique."
IBM Technical Disclosure Bulletin, vol. 14, No. 12, pp. 3640-3641, May 1972, U. Baitinger et al., "Monolithic Storage Cell with FETs."
IBM Technical Disclosure Bulletin, vol. 17, No. 11, pp. 3338-3339, Apr. 1975, H. Linton et al., "Low-Power FET Storage Cell."
IBM Technical Disclosure Bulletin, vol. 31, No. 1, p. 291, Jun. 1988, W. D. Loehlein et al., "Combined Single/Dual-Port Array Approach with 6-Device Cell."
IEEE Journal of Solid-State Circuits article, vol. SC-20, No. 5, pp. 1012-1017, Oct. 1985, H. Takahashi et al., "A 240K Transistor CMOS Array with Flexible Allocation of Memory and Channels."
IEEE Journal of Solid-State Circuits article, vol. SC-22, No. 4, pp. 616-619, Aug. 1987, H. De Los Santos et al., "On the Analysis and Design of CMOS-Bipolar SRAM'S."
IEEE Journal of Solid-State Circuits article, vol. SC-22, No. 5, pp. 847-849, Oct. 1987, S. Miyaoka et al., "A 7-ns/350-mW 64-kbit ECL-Compatible RAM."
IEEE Journal of Solid-State Circuits article, vol. SC-22, No. 5, pp. 657-662, Oct. 1987, G. Kitsukawa et al., "An Experimental 1-Mbit BiCMOS DRAM."
IEEE Journal of Solid-State Circuits article, vol. SC-22, No. 5, pp. 712-720, Oct. 1987, K. O'Connor, "The Twin-Port Memory Cell."
IEEE Journal of Solid-State Circuits article, vol. 23, No. 1, pp. 68-73, Feb. 1988, T. Douseki et al., "BICMOS Circuit Technology for a High-Speed SRAM."
IEEE Journal of Solid-State Circuits article, vol. 23, No. 5, pp. 1030-1039, Oct. 1988, T-S Yang et al., "A4-ns 4Kx1-bit Two-Port BICMOS SRAM."
IEEE Journal of Solid-State Circuit Conference Proceedings, pp. 132-133, Feb. 26, 1987, S. Miyaoka et al., "A 7ns/350-mW 64 EC1 Compatible RAM."
Intel Memory Components Handbook article, pp. 3-38 to 3-45, Mar. 1980, J. Altnether, "High Speed Memory System Design Using 2147H."

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