Static information storage and retrieval – Systems using particular element – Molecular or atomic
Reexamination Certificate
2000-03-14
2001-11-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Systems using particular element
Molecular or atomic
C365S182000
Reexamination Certificate
active
06320784
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices and more particularly to semiconductor device memory cells.
RELATED ART
As semiconductor scaling continues, integration problems are encountered which can affect the performance and reliability of semiconductor devices. For non-volatile memory (NVM) devices, such as electrically erasable programmable random access memories (E
2
PROMs) these can include leakage or loss of the charge stored in the memory cell's floating gate from thinning of the device's tunnel oxide.
Quantum dot (nanocrystal) technology is an area currently under investigation as a replacement for conventional floating gates in scaled NVM devices. One specific application uses singularly isolated silicon nanocrystals as discrete storage elements to store the charge in the floating gate. The isolated nature of each of the nanocrystals reduces the floating gate's vulnerability to charge leakage that results from defects in the underlying tunnel oxide. Instead of providing a leakage path for the entire floating gate, the defect(s) provide a leakage path only for individually charged nanocrystals. Typically, the charge leakage from a single nanocrystal will not affect the overall charge associated with the floating gate.
The charge on the floating gate nanocrystals can be used to regulate the conductivity of the underlying channel in the NVM semiconductor device. The two states of the nanocrystal floating gate, which include nanocrystals uncharged and nanocrystals charged to an average uniform density (in electrons per nanocrystal) can be distinguished by the observed conductivity change in the memory's channel which manifests itself as a threshold voltage (V
T
) shift.
Two important device parameters for NVM nanocrystal floating gates include the V
T
shift magnitude and the charge retention time. The V
T
shift magnitude between the uncharged state and the charged state depends on the average number of electrons injected per nanocrystal during the write operation. The greater the average number of electrons stored, the greater the V
T
shift. Moreover, a corresponding ability to detect the V
T
shift also increases with the number of electrons stored in the nanocrystal.
However, coulomb repulsion effects can be significant in nanocrystals, and coulomb charging energy can limit injection of electrons into the nanocrystal. For a given write operation pulse, there is a saturation of the number of electrons that are accommodated in the nanocrystal. As soon as a first electron is injected into the nanocrystal, subsequently injected electrons encounter coulombic repulsion from the negatively charged nanocrystal and tend to leak out. Thus, the retention time of the subsequently injected electron(s) is reduced. Therefore, at a given tunnel oxide thickness, the prior art is incapable of increasing a nanocrystal's V
T
shift without adversely affecting the charge retention time associated with the nanocrystal.
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Sandip Tiwari et al., “Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage”, 1995 IEDM/IEEE, pp. 20.4.1 thru 20.4.4.
Sandip Tiwari et al, “A silicon nanocrystals based memory”, Mar. 4, 1996 American Institute of Physical, vol. 68, No. 10, pp. 1377-1379.
Jiang Bo
Madhukar Sucharita
Muralidhar Ramachandran
O'Meara David L.
Sadd Michael Alan
Ho Hoai V.
Motorola Inc.
Nelms David
Rodriguez Robert A.
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