Memory cell and method for manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Junction field effect transistor

Reexamination Certificate

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Details

C257S264000, C257S302000, C257S334000

Reexamination Certificate

active

07342264

ABSTRACT:
The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory cell comprises a straddle gate, a carrier trapping structure and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping structure is located between the straddle gate and the substrate, wherein the carrier trapping structure comprises a trapping layer directly in contact with the straddle gate and a tunnel layer located between the trapping layer and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

REFERENCES:
patent: 6657252 (2003-12-01), Fried et al.
patent: 6831310 (2004-12-01), Mathew
patent: 7075148 (2006-07-01), Hofmann et al.
patent: 7119384 (2006-10-01), Popp et al.
“Multilevel Vertical-Channel SONOS Nonvolatile Memory on SOI” By Yong Kyu Lee et al. / IEEE Devices Letters, vol. 23, No. 11, Nov. 2002 / pp. 664-666.
“A Novel MNOS technology Using Gate Hole Injection in Erase Operation for Embedded Nonvolatile Memory Applications” By F. Ito et al. / 2004 Symposium on VLSI Technology Digest of Technical papers / pp. 80-81.
“Novel Dual Bit Tri-Gate Charge Trapping Memory Devices” By M. Specht et al. / IEEE Electron Device Letters, vol. 25, No. 12, Dec. 2004 / pp. 810-812.

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