Memory cell

Details Memory cell Memory cell

1999-11-18

2001-09-04

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having fuse element

Reexamination Certificate

active

06285619

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to memory cells which use fuses to permanently store data in integrated circuits.
FIG. 1
shows an exemplary memory cell
10
for storing one bit of data in an integrated circuit. The stored bit may be part of a chip identification number, may indicate to a decoder whether a redundant circuit should be used in place of a main circuit, may store a default value to be used by control circuitry of the integrated circuit, or may be used for a variety of other purposes.
Memory cell
10
includes a fuse
12
and a latch
14
. Fuse
12
stores the bit of data. During power-up of the integrated circuit, the information stored by fuse
12
is read by the circuitry to which the information applies. To read the information during power-up, a recharging signal (bFPUP) first recharges latch
12
. Next, a read signal (FPUN) cause the information stored in fuse
12
to be output as the BIT signal. If fuse
12
is not blown, the FPUN signal causes node N to be grounded and, hence, causes the BIT signal to be high. If fuse
12
is blown, node N remains high which causes the BIT signal to be low.
FIG. 2
shows an exemplary integrated circuit lay out for two adjacent memory cells of the type shown in FIG.
1
. Each one of these memory cells can use, for example, a six transistor latch
14
to store and allow reading a single bit of data. In some implementations, each one of the latches
14
occupies close to 1.5 times the layout area required by a single fuse
12
. In addition, each one of latches
14
can increase the pitch of memory cell
10
(that is, the minimum required space between adjacent memory cells) to be more than that required by fuse
12
.
Referring to
FIG. 3
, in a highly integrated circuit, thousands of fuse and latch memory cells may be used. To read them during power-up, significant current is required. Such a high current can damage the integrated circuit. Hence, instead of reading all of the memory cells at the same time, the memory cells in the integrated circuit are organized into memory cell banks which are then read sequentially according to a predetermined sequence. In
FIG. 3
, for example, line
14
shows the sequence by which memory cell banks BK are read. To implement the sequence, buffers are used to delay the bFpup and FPUN signals from one memory cell bank to the next. These buffers require additional space on the integrated circuit chip.
SUMMARY OF THE INVENTION
In one general aspect, the invention features a circuit for storing a bit of data, where the circuit includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown.
Hence, according to the invention, two fuses can be used to store a bit of information.
In another aspect the invention features an integrated circuit which includes a first circuit and a second circuit. The first circuit stores a bit of data and includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown. The second circuit has an input connected said common input to read said stored bit of information.
In yet another aspect, the invention features an array for storing bits of data. The array includes a plurality of circuits for storing the bits of data, including a circuit which includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store a bit of data, one of the first and second fuses is selectively blown.
Preferred embodiments of the invention may include one or more of the following features.
A long-channel MOS transistor is provided where one of the source and drain is connected to the first end of the first fuse and the other one of the source and drain is connected to a power supply for providing a voltage corresponding to either logic 1 or logic 0. The first and third ends can be connected to the common output through an inverter. The fuses may be laser or electrical fuses.
Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, suitable methods and materials are described below. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety. In case of conflict, the present specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and not intended to be limiting.


REFERENCES:
patent: 5208775 (1993-05-01), Lee
patent: 5579266 (1996-11-01), Tahara
patent: 5689465 (1997-11-01), Sukegawa et al.
patent: 5696723 (1997-12-01), Tukahara
patent: 5898626 (1999-04-01), Chiang et al.
patent: 5910921 (1999-06-01), Beffa et al.
patent: 5933382 (1999-08-01), Yi et al.

Affiliated with

Also associated with

Rating

Memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2462693