Memory cell

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S302000, C257S315000, C257S330000, C438S270000

Reexamination Certificate

active

10913707

ABSTRACT:
In a memory cell, in a trench, a layer sequence comprising a first oxide layer, a nitride layer provided on the first oxide layer, and a second oxide layer, facing the gate electrode, and provided at the lateral trench walls, while the nitride layer is absent in a curved region of the trench bottom. In an alternative configuration, in each case at least one step is formed at the lateral walls of the trench, preferably below the source region or the drain region, respectively.

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patent: 5252845 (1993-10-01), Kim et al.
patent: 5424231 (1995-06-01), Yang
patent: 6191459 (2001-02-01), Hofmann et al.
patent: 6309924 (2001-10-01), Divakaruni et al.
patent: 6469345 (2002-10-01), Aoki et al.
patent: 2001/0008291 (2001-07-01), Aoki et al.
patent: 2002/0024092 (2002-02-01), Palm et al.
patent: 2003/0015752 (2003-01-01), Palm et al.
patent: 100 39 441 (2002-02-01), None
patent: 100 41 749 (2002-03-01), None
patent: 4-12573 (1992-01-01), None

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