Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1997-03-31
2001-03-13
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C361S689000, C361S788000
Reexamination Certificate
active
06202110
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to computer memory construction, and more particularly to memory cards arranged to be mounted back-to-back on a backplane board.
Computer systems are designed to meet an ever-increasing demand to operate memory and processor busses at higher and higher frequencies. One feature which is used to meet these requirements is the use of an active backplane, i.e., circuitry which functions as both memory control and as a bridge between the CPU bus and the I/O bus is mounted directly on the backplane or motherboard. This circuitry buffers and routes data between various devices on the processor and I/O busses as well as maintains the coherency of cacheable data. Because this memory controller and bridge circuitry communicates with processor, memory and I/O subsystems, it resides on the backplane, centered between the main busses (processor bus, memory bus, I/O bus) to minimize the lengths of interconnect wires. The CPU is mounted on a daughter card, and the memory devices (SIMMs or DIMMs) are also mounted on daughter cards. These daughter cards are mounted at right angles to the backplane or motherboard, in connector slots.
To accommodate additional memory, a backplane is usually designed to support multiple memory cards. For example, there may be two slots for mounting two memory cards, in a typical construction, and these two memory cards are mounted in a front-to-back arrangement, i.e., both facing the same way. When laying out the backplane with this type of memory card, sufficient separation must be maintained between edge connectors for the cards to accommodate clearance required for the SIMMs or DIMMs which extend at right angles from the memory cards. This separation distance between memory cards adds to the overall length of the path for each memory data, address and control signal between the memory controller and the memory cards. The increased path length contributes to the RC wire delay, which increases the memory bus cycle time, degrading overall memory bandwidth and system performance. In one example of a typical contemporary construction, using connectors made by AMP called High Speed Card Edge Connectors (HSCE), with 200-pin SDRAMs Memory DIMMs (JEDEC standard number 21-C of JC42.5), and nominal memory card thickness of 0.070 inch, allowing 0.170 inch for card sway, yields a card separation of 1.50 inches. With typical propagation delays of printed circuit card wires at 180 picoseconds per inch, the 1.50 inches of card wire contributes at least 270 picoseconds of delay to each memory net.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved computer construction.
It is another object of the present invention to provide an improved memory card arrangement to reduce memory access time in a computer.
It is a further object of the present invention to provide an improved method of mounting memory cards in a computer system to reduce the spacing between cards and reduce the overall size of the system.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
According to one embodiment of the invention, memory cards for a computer system can be placed back-to-back on an active backplane, using wiring topology where the memory address and data busses are wired to pairs of symmetrical connectors. This topology takes advantage of symmetrical memory card pinouts to improve memory bus performance while reducing backplane cost and wiring complexity. The symmetrical layout of the data and address wiring allows two memory cards to be placed back-to-back on the backplane, maintaining the same relative position of data and address pins between cards. Since the data and most of the address buses are common to each card, and any such data or address pin (that is common or non-unique) on one card can be wired to any other such data or address pin, respectively, on the other card, the back-to-back arrangement provides for minimal address and data bus interconnect lengths between connectors. Each data signal can be wired from a memory controller data pin on the first connector, then daisy-chained through the short printed circuit card wire to an adjacent pin on the second connector. Likewise, non-unique address pins can be connected from the memory controller to address pins that are parallel between connectors. Those unique address and control signals which are to be connected together are placed as close as possible to the centerpoint of the edge connector. In the example given above, the memory connector pitch can be reduced to 0.50 inch, compared to 1.50 inch in the prior construction. Signal propagation delay is reduced by a factor of three from the conventional front-to-back orientation. Backplane wiring complexity and cost are also reduced. The short, parallel daisy-chained interconnects between connector pins reduce the need for many board wiring layers for interconnecting the data and address busses. The reduced layer count, along with the board area savings resulting from placing the two connector slots as close as possible, serve to reduce the raw card component cost.
REFERENCES:
patent: 5119486 (1992-06-01), Albonesi
patent: 5463755 (1995-10-01), Dumarot et al.
patent: 5754796 (1998-05-01), Wang et al.
patent: 5926378 (1999-07-01), DeWitt et al.
patent: 6058442 (2000-05-01), Fort
Coteus Paul William
Mirabella Robert Dominick
Auve Glenn A.
Emile Volel
Felsman Bradley Vaden Gunter & Dillon, LLP
International Business Machines - Corporation
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