Memory card interface method using multiplexed storage...

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol

Reexamination Certificate

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Details

C711S164000, C711S115000

Reexamination Certificate

active

06182174

ABSTRACT:

FIELD OF THE INVENTION
This invention is related to computers and computer system memories and in particular to the interfaces between a memory controller and memory card of an S/390 system computer system memory.
BACKGROUND
Any mainframe such as a S/390 compatible system, which uses a storage protection (SP) key and uses a command response (handshake) type bus between the processor and memory, provides an interface to memory or main store. Processor to memory (or Main Store MS) interfaces have always existed in the computer industry. There are many ways to define the communication protocol or handshake between the sender and receiver on both sides of the bus for memory accesses. A typical example of processor to memory protocol includes Command Accept, Fetch Data Alert, Store Complete with additional protocols for bus management if the data bus is a bi-directional bus.
These protocols may require separated hardware signals or the protocol may be embedded with an existing bus and time shared control signals are passed with other existing signals like data bus or command bus signals. These other solutions require extra hardware signal lines and/or restrict the performance in order to mix with control signals on an existing bus which can handle the interface handshake. Separated hardware signals means more hardware lines and more input/output (IO) from chips and modules. Timing sharing with other signals also presents a restriction and limits functional usage.
SUMMARY OF THE INVENTION
This invention provides a way for the S/390 memory card to return its SP key data as an indication the command was “accepted” by the memory card while the SP key is returned to the requestor for storage validation. Had the memory card detected an error, it would have indicated an error status response using the same bus. Therefore, we multiplex the Key Return, Command Acceptance, Error Reporting, and Data Return onto one Memory Status Bus without having separate signal lines for all these conditions.
By using an existing architected function, the SP key communication protocol and the memory command response protocol are merged together, providing support for each function without exposure to any control restriction or performance limitation.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.


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Ekanadham et al, “Multisequencing A Single Instruction Stream-Storage Protect Key Register,” IBM Tech. Disc. Bull., vol. 36, No. 6A, Jun. 1993, pp. 269-271.

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