Electrical computers and digital data processing systems: input/ – Intrasystem connection – Protocol
Reexamination Certificate
1998-04-13
2001-01-30
Gossage, Glenn (Department: 2759)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Protocol
C711S164000, C711S115000
Reexamination Certificate
active
06182174
ABSTRACT:
FIELD OF THE INVENTION
This invention is related to computers and computer system memories and in particular to the interfaces between a memory controller and memory card of an S/390 system computer system memory.
BACKGROUND
Any mainframe such as a S/390 compatible system, which uses a storage protection (SP) key and uses a command response (handshake) type bus between the processor and memory, provides an interface to memory or main store. Processor to memory (or Main Store MS) interfaces have always existed in the computer industry. There are many ways to define the communication protocol or handshake between the sender and receiver on both sides of the bus for memory accesses. A typical example of processor to memory protocol includes Command Accept, Fetch Data Alert, Store Complete with additional protocols for bus management if the data bus is a bi-directional bus.
These protocols may require separated hardware signals or the protocol may be embedded with an existing bus and time shared control signals are passed with other existing signals like data bus or command bus signals. These other solutions require extra hardware signal lines and/or restrict the performance in order to mix with control signals on an existing bus which can handle the interface handshake. Separated hardware signals means more hardware lines and more input/output (IO) from chips and modules. Timing sharing with other signals also presents a restriction and limits functional usage.
SUMMARY OF THE INVENTION
This invention provides a way for the S/390 memory card to return its SP key data as an indication the command was “accepted” by the memory card while the SP key is returned to the requestor for storage validation. Had the memory card detected an error, it would have indicated an error status response using the same bus. Therefore, we multiplex the Key Return, Command Acceptance, Error Reporting, and Data Return onto one Memory Status Bus without having separate signal lines for all these conditions.
By using an existing architected function, the SP key communication protocol and the memory command response protocol are merged together, providing support for each function without exposure to any control restriction or performance limitation.
These and other improvements are set forth in the following detailed description. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.
REFERENCES:
patent: 4038645 (1977-07-01), Birney et al.
patent: 4366537 (1982-12-01), Heller et al.
patent: 4500952 (1985-02-01), Heller et al.
patent: 5163096 (1992-11-01), Clark et al.
patent: 5499346 (1996-03-01), Amini et al.
patent: 5634015 (1997-05-01), Chang et al.
patent: 5828835 (1998-10-01), Isfeld et al.
Ekanadham et al, “Multisequencing A Single Instruction Stream-Storage Protect Key Register,” IBM Tech. Disc. Bull., vol. 36, No. 6A, Jun. 1993, pp. 269-271.
Kark Kevin W.
LaVallee Russell W.
Lipponer Walter
Shen William Wu
Ulland Hartmut
Augspurger Lynn L.
Gossage Glenn
International Business Machines - Corporation
LandOfFree
Memory card interface method using multiplexed storage... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory card interface method using multiplexed storage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory card interface method using multiplexed storage... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2445975