Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus expansion or extension
Reexamination Certificate
2000-02-02
2003-11-04
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus expansion or extension
C710S107000, C710S269000, C711S100000, C711S103000, C714S042000, C714S043000, C712S208000
Reexamination Certificate
active
06643725
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory cards such as file memories, and relates to a technique advantageously applied to, for example, a memory card in which functions of a file memory is included on a single chip.
2. Description of the Related Art
A file memory is a memory card capable of storing file data utilizing a technique similar to management of file allocation by using an FAT (file allocation table) in a hard disk. For example, an electrically rewritable flash memory is used as file data storage area in such a file memory. When file data are accessed, the data are temporarily stored in a buffer memory. For example, file data to be written stored in the buffer memory are written in the flash memory after being assigned with an ECC code at an ECC circuit, and file data read from the flash memory and stored in the buffer memory are output to the outside after error check and correction using an ECC code.
A file memory frequently incorporates a data processor such as a microcomputer for purposes including file management and control of access to the buffer memory.
PCMCIA-ATA type flash memory cards which are one type of file memories are described on pages 78 and 79 of “Nikkei Electronics” published on Apr. 11, 1994.
SUMMARY OF THE INVENTION
The inventors conducted a study on a control program area of a file memory having a data processor. A file memory requires a program for debugging or testing in addition to a program for normal file management. The required programs are normally incorporated in a memory card even when the file memory incorporates a data processor, such as a microprocessor, because such a data processor does not need a function of accessing outside the memory card. The storage capacity of a ROM for storing programs is thus increased by the program for debugging and testing, and the like, which results in a problem in that the scale of the circuit is increased. Thus, the inventors recognized that a countermeasure is needed when limitations placed upon chip size, and the like, do not allow a random increase of the storage capacity of a ROM in implementing functions of a memory card such as a file memory in the form of a semiconductor integrated circuit by loading them on a single chip.
It is an object of the invention to provide a memory card in which a data processor incorporated therein can be caused to execute new programs for purposes including testing or debugging without adding a separate program memory.
The above and other objects and novel features of the invention will become apparent from the description of this specification and the accompanying drawings.
Typical aspects of the invention disclosed in this application can be summarized as follows.
There is provided a memory card
1
comprising an electrically rewritable non-volatile memory
4
, a data processor
3
having a function of executing instructions capable of managing the allocation of file data in the non-volatile memory, an interface control circuit
2
having a function of establishing external interface, for controlling the execution of instructions by the data processor in response to external commands and for controlling access to the non-volatile memory and a buffer memory
7
for temporarily storing the file data, in which the buffer memory can be used also as a program memory. Specifically, there is provided command control means
24
,
26
for decoding a first command CMD
1
supplied from the outside and for instructing the data processor to fetch an instruction from the buffer memory and to operate. This makes it possible to cause the integrated data processor to execute new programs for purposes including testing or debugging without adding a separate program memory.
Interrupt may be used as a method of control for causing the data processor to execute a program PGM
1
stored in the buffer memory. In this case, the command control means may employ a configuration in which an interrupt is requested to the data processor and a first cause of interrupt is notified to the same by decoding the first command.
When vector control is used as a method for controlling the interrupt, the data processor includes a central processing unit
30
capable of responding to an interrupt by transferring the process to an instruction address indicated by a vector retrieved from a vector table
340
according to the cause of interrupt and a ROM
34
to be accessed by the central processing unit. The ROM
34
includes the vector table
340
and a program area
341
, and the vector table includes a first vector VCT
1
associated with the first cause of interrupt. Thus, the central processing unit can execute an instruction from the beginning of the program in the buffer memory indicated by the first vector.
The program PGM
1
may be transferred to the buffer memory from the outside or from the integrated flash memory. The usability of the file memory is improved by allowing the file memory to transfer the program to the buffer memory by itself. For example, when the program PGM
1
is allowed to be stored in the buffer memory from the outside of the file memory, the command control means further requests the data processor an interrupt and notifies it of a second cause of interrupt by decoding a second command CMD
2
supplied from the outside. The vector table in the ROM further includes a second vector VCT
2
that responds to the second cause of interrupt. The program area of the ROM further includes a transfer control program PGM
2
for storing the externally supplied program in the buffer memory starting from a first address thereof. In this case, the second vector is information indicating the leading address of the transfer control program, and the first address is an address that coincides with the address indicated by the first vector VCT
1
.
When the program PGM
1
is allowed to be stored in the buffer memory from the non-volatile memory incorporated in the file memory, the command control means further requests the data processor an interrupt and notifies the same of a third cause of interrupt by decoding a third command CMD
3
supplied from the outside. The vector table in the ROM further includes a third vector VCT
3
that responds to the third cause of interrupt. The program area of the ROM further includes a transfer control program PGM
3
for storing the program supplied from the non-volatile memory in the buffer memory starting from the first address thereof. In this case, the third vector is information indicating the leading address of the transfer control program, and the first address is an address that coincides with the address indicated by the first vector.
In the memory card
1
constituted by a single chip, even when a random increase of the storage capacity of the ROM is inhibited by limitations on the chip size and the like, the programs for purposes including debugging or testing can be executed within the limitations.
REFERENCES:
patent: 4126896 (1978-11-01), Yamazaki
patent: 4504915 (1985-03-01), Daniels et al.
patent: 4760518 (1988-07-01), Potash et al.
patent: 5138619 (1992-08-01), Fasang et al.
patent: RE34445 (1993-11-01), Hayes et al.
patent: 5291603 (1994-03-01), Morse et al.
patent: 5404915 (1995-04-01), Mugge et al.
patent: 5473573 (1995-12-01), Rao
patent: 5535165 (1996-07-01), Davis et al.
patent: 5584044 (1996-12-01), Gouhara et al.
patent: 5598368 (1997-01-01), Takahashi et al.
patent: 5704058 (1997-12-01), Derrick et al.
patent: 5802551 (1998-09-01), Komatsu et al.
patent: 5887187 (1999-03-01), Rostoker et al.
patent: 6000048 (1999-12-01), Krishna et al.
M. Morris Mano, Computer System Architecture, 1982, Prentice-Hall, Inc., 2nd edition, pp. 159-161, 261-263, 434-443.*
Webopedia's definition on the vector, http://www.webopedia.com/term/v/vector.html.*
Webopedia's definition on the EEPROM, http://www.webopedia.com/term/E/EEPROM.html.*
Nikkei Electronics, Apr. 11, 1994.
Furusawa Kazunori
Jono Yuusuke
Kanamori Motoki
Kozakai Kenji
Shikata Atsushi
Hitachi , Ltd.
King Justin
Mattingly Stanger & Malur, P.C.
Ray Gopal C.
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