Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-12-04
2007-12-04
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S719000
Reexamination Certificate
active
10484043
ABSTRACT:
In the initial setting of a memory card1, the flash check data FD stored in a flash memory2is read out, this data FD is compared with the operation check data FD11stored previously in the ROM, the write check data FD12stored in the ROM4ais written, if a fault is not detected, to the flash memory2, and this data is read again and is compared with the write check data FD12of the ROM4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory2is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register5ato set a controller3to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
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Kanamori Motoki
Katayama Kunihiro
Kurakata Shigeo
Oodate Hidefumi
Shiraishi Atsushi
Baderman Scott
Hitachi ULSI Systems Co. Ltd.
Lohn Joshua
Miles & Stockbridge P.C.
Renesas Technology Corp.
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