Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2007-11-13
2007-11-13
Sparks, Donald (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S008000, C710S049000, C714S025000, C717S168000, C717S171000
Reexamination Certificate
active
10549614
ABSTRACT:
Whether an initial command outputted from a host is ‘CMD1’or ‘CMD55+CMD41’is detected with an initial command detection portion8, and the result of detection is set in an SD/MMC register13. Reset process for hardware and that for firmware are carried out based on the result of detection set in the SD/MMC register13. Thereafter, a microcomputer7sets data indicating in which mode, MultiMedia Card mode or SD mode, the firmware reset process was carried out, in a F/W process SD/MMC register14. A H/W-F/W mode comparison circuit15compares data in the SD/MMC register13with data in the F/W process SD/MMC register14. If these data agree with each other, busy state is released, and command wait state is established. If they disagree with each other, a disagreement occurrence detection signal is outputted to the microcomputer7, and power-on reset processing is performed again.
REFERENCES:
patent: 6708231 (2004-03-01), Kitagawa
patent: 2001/0000405 (2001-04-01), Gray et al.
patent: 2004/0064686 (2004-04-01), Miller et al.
patent: 6-187133 (1994-07-01), None
patent: 2003-30613 (2003-01-01), None
Kanamori Motoki
Kumahara Chiaki
Kurakata Shigeo
Odate Hidefumi
Shikata Atsushi
Dews Brooke J
Miles & Stockbridge P.C.
Renesas Technology Corp.
Sparks Donald
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