Memory cache bank prediction

Electrical computers and digital processing systems: memory – Address formation – Address mapping

Reexamination Certificate

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Details

C711S213000, C711S005000, C711S120000, C711S129000, C711S168000

Reexamination Certificate

active

06880063

ABSTRACT:
A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

REFERENCES:
patent: 5640532 (1997-06-01), Thome et al.
patent: 5752259 (1998-05-01), Tran
patent: 5758142 (1998-05-01), McFarling et al.
patent: 5924117 (1999-07-01), Luick
patent: 5933860 (1999-08-01), Emer et al.
patent: 5953747 (1999-09-01), Steely, Jr. et al.
patent: 6005592 (1999-12-01), Koizumi et al.
patent: 6173333 (2001-01-01), Jolitz et al.
patent: 6189083 (2001-02-01), Snyder, II
patent: 6694421 (2004-02-01), Yoaz et al.

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