Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2005-04-12
2005-04-12
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S213000, C711S005000, C711S120000, C711S129000, C711S168000
Reexamination Certificate
active
06880063
ABSTRACT:
A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
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Erez Mattan
Jourdan Stephan J.
Rappoport Lihu
Ronen Ronny
Valentine Bob
Intel Corporation
Kenyon & Kenyon
Peikari B. James
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