Memory bypass with support for path delay test

Details Memory bypass with support for path delay test Memory bypass with support for path delay test

2002-12-26

2008-10-21

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S726000, C714S729000

Reexamination Certificate

active

07441164

ABSTRACT:
A method and apparatus are described for testing at least one critical data path in a design of a digital integrated circuit chip during a simulation of the design. A dedicated memory-bypass-enable signal is provided to a memory-bypass-logic circuit of the design during test modes of the simulation. Data content of a memory circuit within the critical data path is protected, using the dedicated memory-bypass-enable signal, during part of a path-delay test mode of the simulation. The memory circuit is also bypassed using the memory-bypass-enable signal during a memory-bypass test mode of the simulation.

REFERENCES:
patent: 5124946 (1992-06-01), Takahashi
patent: 5761215 (1998-06-01), McCarthy et al.
patent: 6587996 (2003-07-01), Reohr et al.

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