Memory bypass mode

Details Memory bypass mode Memory bypass mode

1996-09-10

1997-03-18

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

365201, G11C 700

Patent

active

056129165

ABSTRACT:
A bypass mode for an SRAM permitting data to be coupled from the write drivers to the sense amplifier without being written into the cells. The bypass mode is used during testing and is implemented by simultaneously activating the write drivers and sense amplifiers while inhibiting selection of any of the cells in the array. In effect the bitlines in the array are used as bus lines for directly coupling data through the array. The bypass mode eliminates the need for the lines used to couple a bit pattern to a compare circuit during testing thereby saving substrate cover.

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