Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2007-01-09
2007-01-09
Kim, Hong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S141000, C710S105000
Reexamination Certificate
active
10788315
ABSTRACT:
Within a coherent multi-processing system multiple processor cores4, 6are coupled via respective memory buses to a memory access control unit16. The memory buses are formed of a uni-processing portion containing signals specifying a memory access request in accordance with a uni-processing protocol. This uni-processing bus is augmented by a multi-processing bus containing signals giving additional information concerning memory access requests which may be used by the memory access control unit to service those requests and manage coherency within the system.
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Biles Stuart David
Lataille Norbert Bernard Eugéne
Pruvost Julie-Anne Francoise Marie
ARM Limited
Kim Hong
Nixon & Vanderhye P.C.
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