Memory bus termination with memory unit having termination...

Details Memory bus termination with memory unit having termination... Memory bus termination with memory unit having termination...

2005-12-27

2005-12-27

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C711S105000

Reexamination Certificate

active

06981089

ABSTRACT:
Methods and apparatus for a memory system using line termination circuits in each memory unit (e.g., integrated circuit memory device) are disclosed. The memory unit contains termination control logic that sets the state of a controllable termination circuit to control reflections on the data bus. The termination control logic determines the proper state for the termination circuit from the state of its memory unit, and in some cases, from the approximate state of the data bus as gleaned from commands decoded from the command/address bus. A termination configuration register on the unit can be used to define the appropriate termination state for each unit state and/or data bus state.

REFERENCES:
patent: 5604714 (1997-02-01), Manning et al.
patent: 6304502 (2001-10-01), Watanabe et al.
patent: 6349051 (2002-02-01), Klein
patent: 6496945 (2002-12-01), Cepulis et al.
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