Memory bus interface

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C712S040000, C713S375000

Reexamination Certificate

active

07103701

ABSTRACT:
An interface allows communication between a host device coupled to a host bus and a target device coupled to a target bus. First, the interface receives the address of the target device from the host device via the host bus, where the address has a first width. Next, the interface converts the received address from the first width into one or more address components each having a second width. Then, the circuit accesses the target device by driving the one or more address components onto the target bus. Such an interface allows for a simple, direct communication path between the host bus, such as a system bus, and a target bus, such as an LPC bus. The interface consolidates several tasks into one general purpose interface, providing savings in components used, design complexity, and overall cost of implementation. Further, the length of time required for communications between interfaced busses is substantially reduced.

REFERENCES:
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patent: 6421765 (2002-07-01), Poisner
patent: 6434654 (2002-08-01), Story et al.
patent: 6851014 (2005-02-01), Chang et al.
patent: 2001/0029560 (2001-10-01), Delchini
French Search Report dated Feb. 4, 2004.

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