Memory bus checking procedure

Details Memory bus checking procedure Memory bus checking procedure

2006-04-25

2006-04-25

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Transmission facility testing

Reexamination Certificate

active

07036054

ABSTRACT:
A method for checking usable width of a data bus linking a host device and a memory card. Preferably, at the boot up process the host device sends a test bit pattern to the memory card through the data bus. The test bit pattern can be (1010 . . . ) or (0101 . . . ). Upon receiving the test bit pattern, the memory card sends a response bit pattern to the host device through the same data bus. The response bit pattern is complement to the test bit pattern so as to allow the host device to compare the response bit pattern with the test bit pattern, and determines the usable width of the data bus based on the comparison result.

REFERENCES:
patent: 6473871 (2002-10-01), Coyle et al.
patent: WO 02/15020 (2002-02-01), None

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