Memory bus arbitration using memory bank readiness

Details Memory bus arbitration using memory bank readiness Memory bus arbitration using memory bank readiness

2006-08-04

2008-09-16

Song, Jasmine (Department: 2188)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S151000, C711S158000, C710S039000, C710S240000, C710S244000

Reexamination Certificate

active

07426603

ABSTRACT:
A method, apparatus, and computer program product includes identifying a plurality of memory transactions to be sent over a memory bus to a memory having a plurality of memory banks, each memory transaction addressed to one of the memory banks, the memory bus incapable of transmitting the plurality of memory transactions simultaneously; identifying a plurality of bank readiness signals, each bank readiness signal indicating the readiness of one of the memory banks to accept a memory transaction; and selecting one of the memory transactions for transmission over the memory bus based on the bank readiness signals.

REFERENCES:
patent: 6381686 (2002-04-01), Imamura
patent: 6591349 (2003-07-01), Steinman et al.
patent: 6598132 (2003-07-01), Tran et al.
patent: 6622225 (2003-09-01), Kessler et al.
patent: 7076617 (2006-07-01), Dodd

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