Patent
1994-01-28
1996-08-13
Harvey, Jack B.
395293, G06F 1300
Patent
active
055465471
ABSTRACT:
An arbitration scheme for a computer system in which a digital signal processor resides on the computer system's memory bus without requiring a block of dedicated static random access memory. An arbitration cycle is divided into 10 slices of which 5 slices are provided in each arbitration loop to the digital signal processor. Two slices are provided each to the system's I/O interface and to the peripheral bus controller. A final slice is provided to the system's CPU. A default state when no memory bus resource is requesting the system memory bus parks the memory bus on the CPU. The arbitration scheme provides sufficient bandwidth for real-time signal processing by the digital signal processor operating from the system's dynamic random access memory while also providing sufficient bandwidth for a local area network interface through the system's I/O interface.
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Bowes Michael J.
Yazdy Farid A.
Apple Computer Inc.
Harvey Jack B.
Wiley David A.
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