Memory bus address snooper logic for determining memory activity

Details Memory bus address snooper logic for determining memory activity Memory bus address snooper logic for determining memory activity

1996-11-26

1999-05-04

Dinh, Dung C.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

39520043, 39520044, 711146, G06F 1300, G06F 1314, G06F 1516

Patent

active

059013265

ABSTRACT:
A parallel multiprocessor data processing system having a plurality of nodes for processing data and a switch connected to each of said nodes for switching messages between the nodes, each node having a node processor for defining messages under program control to be sent to another node. Each of the nodes has an I/O processor for controlling the sending of messages to another node via the switch, and a shared memory which can be accessed by both the node processor and the I/O processor. Instructions for the messages to be sent by the I/O processor are stored in mailboxes in the shared memory by the node processor. A comparing circuit compares addresses on the bus to the contents of a plurality of address registers and sets the corresponding bit in a results register for each match. The adapter processor reads the contents of the results register such that the adapter processor may, with a single bus access, determine all mailboxes that have been accessed by the node processor.

REFERENCES:
patent: 4783730 (1988-11-01), Fischer
patent: 5404489 (1995-04-01), Woods et al.
patent: 5410654 (1995-04-01), Foster et al.
patent: 5428761 (1995-06-01), Herlihy et al.
patent: 5502828 (1996-03-01), Shah
IBM Technical Disclosure Bulletin, vol. 32, No. 11, Apr. 1990, pp. 170-171 "Snoop Mechanism To Monitor Computer Bus".

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