Memory bits used to couple look up table inputs to facilitate in

Details Memory bits used to couple look up table inputs to facilitate in Memory bits used to couple look up table inputs to facilitate in

1997-04-01

1999-05-18

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, H03K19/177

Patent

active

059053852

ABSTRACT:
A field programmable gate array (FPGA) with pass gates included in configurable logic block (CLB) circuitry to enable look up tables (LUT) inputs to be selectively tied together when a larger LUT is desired, or simply if it is desirable for particular LUT inputs to be identical. Since LUT inputs may be tied together, circuitry is also included to more effectively utilize configuration block multiplexers (CBLOCK MUXs) no longer needed to provide LUT inputs. In one embodiment, with LUT inputs tied together to form a larger LUT, circuitry is provided so that the select input of a MUX in the larger LUT is provided from one of the CBLOCK MUXs which is freed up. In another embodiment, the gates of pass gates connecting LUT inputs together, as well as the gates of other pass gate used for configuring other circuitry in the LUTs may be controlled from a single memory cell.

REFERENCES:
patent: 5260881 (1993-11-01), Agrawal et al.
patent: 5386156 (1995-01-01), Britton et al.
patent: 5488316 (1996-01-01), Freeman et al.
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5559450 (1996-09-01), Ngai et al.
patent: 5815003 (1998-09-01), Pedersen
patent: 5815726 (1998-09-01), Cliff
"The Programmable Logic Data Book", Xilinx, pp. 2-9 through 2-24, 1994, No Month.

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