Memory bit-line pull-up scheme

Details Memory bit-line pull-up scheme Memory bit-line pull-up scheme

1996-06-28

1997-10-07

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365208, G11C 700, G11C 702

Patent

active

056755422

ABSTRACT:
A method and apparatus for reducing noise in a memory bit-line pull-up circuit. The memory bit-line pull-up circuit includes a first reference line, a second reference line, a first capacitor, a gating device, and a pull-down circuit. The circuit may further include a load transistor coupled between the first reference line and a first voltage conduit, which generally maintains the voltage on the first reference line at Vcc-Vt, and a second capacitor and the load transistor providing a pull-up path for the voltage on the first reference line when Vcc increases and the first capacitor. The pull-down circuit provides a pull-down path for the voltage on the first reference line when Vcc decreases. The first capacitor provides a pull-up path for the voltage on the second reference line. A first gating device couples a bit-line to the first reference line. The circuit further including a second gating device to couple a bit-line bar to the first reference line. By coupling the bit-line(s) to a second reference line through the gating device(s), the gating device(s) are partially turned on during a portion of the bit-line (or bit-line bar) recovery time. In other words, when the voltage on the bit-line (or bit-line bar) is less than the voltage on the reference line, then the coupling of the noise from the bit-line onto the first reference line is generally reduced relative to coupling the bit-line(s) to ground.

REFERENCES:
patent: 5093806 (1992-03-01), Tran
patent: 5508961 (1996-04-01), Han
patent: 5566126 (1996-10-01), Yoshida

Affiliated with

Also associated with

Rating

Memory bit-line pull-up scheme does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory bit-line pull-up scheme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory bit-line pull-up scheme will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2362717