Memory BIST and repair

Details Memory BIST and repair Memory BIST and repair

2001-07-11

2004-07-20

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S030000

Reexamination Certificate

active

06766468

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a memory BIST (Built-In Self Test) and repair, and more particularly pertains to a memory BIST and repair which stores redundancy data on-chip to allow redundancy to be activated during wafer test or to be used to select fuses for permanent enablement (i.e. for e-fuses, which are electrically-blown fuses).
The present invention provides a method of memory BIST (Built-In Self Test) and memory repair that stores a redundancy calculation on-chip, as opposed to scanning this data off-chip for later use. This method no longer requires level-sensitive scan design (LSSD) scanning of memory redundancy data off-chip to the tester, and therefore does not require re-contacting of the chip for electrical fuse blow.
2. Discussion of the Prior Art
Memory BIST and repair is commonly used in memory designs as a means of increasing product yield. BIST and repair schemes in the prior art generally require that the failing bit/word be LSSD (level-sensitive scan design) scanned off-chip or to an on-chip processor to determine fixability of the memory cells and for fuse blow identification.
FIG. 1
illustrates a prior art BIST and repair scheme which requires that the failing bit/word be LSSD scanned off-chip or to an on-chip processor to determine fixability of the memory cells and for fuse blow identification. Also, see U.S. Pat. No. 5,961,653 as an example
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a memory BIST and repair.
A further object of the subject invention is the provision of a memory BIST and repair which stores redundancy data on-chip to allow redundancy to be activated during wafer test or to be used to select fuses for permanent enablement (i.e. for e-fuses).
In accordance with the teachings herein, the present invention provides a method of storing memory redundancy allocation signatures for memory elements, such as memory blocks or banks, on-chip. Pursuant to the method, each memory element capable of redundancy on the chip is interrogated, one at a time using a built-in self test program. A redundancy allocation signature is then stored on the chip for each memory element from said built-in self test program, and redundancy is enabled for each memory element by interpreting the stored redundancy allocation signature for that memory element.


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