Memory based phase locked loop

Details Memory based phase locked loop Memory based phase locked loop

2000-03-30

2003-09-23

Decady, Albert (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S740000, C324S076830, C327S005000, C327S106000, C327S156000

Reexamination Certificate

active

06625765

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a phase locked loops generally and, more particularly, to a memory based phase locked loop.
BACKGROUND OF THE INVENTION
Phase Locked Loops (PLLs) generally comprise the functional blocks of a delay locked loop and an edge corrector/Voltage Controlled Oscillator (VCO). Conventional approaches are to design these components around specialized analog circuits and counters/dividers using digital logic. The important parameters to control are the duty cycle and jitter on the final clock output across process, power supply and temperature variations.
SUMMARY OF THE INVENTION
The present invention concerns a circuit comprising a phase detector/correction circuit, at least one column of memory cells, a control circuit and a sense amplifier. The control circuit may be configured to read a sequence from the memory cells in a predetermined order and present a first output signal. The sense amplifier may be configured to present a periodic signal in response to the first output signal.
The objects, features and advantages of the present invention include providing a phase locked loop that may (i) adjust the frequency of oscillation of the PLL with memory cell(s) that may be “trimmed” with separate memory columns during a test phase, (ii) not require a “warm-up” time to establish locking, (iii) be implemented with a variety of memory cell architectures and/or (iv) implement a wide frequency selector range.


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