Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Patent
1996-05-02
1999-09-07
Bragdon, Reginald G.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
711169, 711158, 711211, 365203, 36523003, 36523006, 36523008, G06F 1200
Patent
active
059502193
ABSTRACT:
A memory 200 comprising a first memory bank 201a including an array 202a of memory cells and a circuitry 203a, 205a for addressing a location within array 202a. Memory 200 further includes a second memory bank 201b including an array 202b of memory cells and circuitry 203b, 205b for addressing location within array 202b. Circuitry 203, 206, 207 is included for selectively pipelining a plurality of serially received words of address bits to the banks 201 during precharge of the banks.
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Bragdon Reginald G.
Cirrus Logic Inc.
Murphy James J.
Shaw Steven A.
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